Semiconductor IP · Early stage
Chip IP, built as software.
IP Nirmaan is an AI-native semiconductor IP company modeled as software: you give it a requirement, and a machine-readable organization plans, routes, reviews, and gates the work, with evidence behind every claim.
Real output
One sentence in. A whole plan out.
What nirmaan plan prints for a 4-port AXI-to-NoC bridge, trimmed. Every task has an owner, and every gate waits for a person’s sign-off.
$ nirmaan plan "Create a 4-port AXI-to-NoC bridge." PROJECT: Create a 4-port AXI-to-NoC bridge Intent: new_ip Features: axi, cdc, multi_port, noc, registers Assumption: Clocking was not stated, so CDC/RDC work is planned conservatively. PROGRAM MANAGER Senior Technical Program Manager ├── Architecture (lead: Chief Architect) │ ├── Interface specification: AXI interface owner: Senior AXI Interface Architect │ ├── Microarchitecture owner: Staff NoC Microarchitect │ └── GATE Architecture approval owner: Chief Architect (human approval) ├── RTL (lead: Director, RTL Engineering) │ ├── RTL implementation: AXI slave interface owner: Senior Interface Design Engineer │ └── RTL implementation: Arbitration owner: Senior Interconnect Design Engineer ├── Verification (lead: VP, Verification) │ ├── Verification plan owner: Senior Verification Planning Engineer │ └── Coverage closure owner: Senior Functional Coverage Engineer └── Signoff └── GATE Verification signoff owner: VP, Verification (human approval)
nirmaan plan, trimmed.The idea
Engineering work, run by an organization you can read.
Three rules the whole system is built on.
-
An organization, not a chatbot.
Divisions, teams, and roles from intern to CEO, each with skills, authority, and an escalation path.
-
Planned is not done.
Work moves through planned, executed, verified, and approved, and nothing skips a step.
-
Evidence or it did not happen.
A tool run, a review, or a named person's sign-off backs every claim. An AI cannot mark its own work approved.
- planned A plan with an owner
- executed Submitted by its owner
- verified All required checks recorded
- approved An authorized sign-off
Refused An AI worker asking to approve its own work is turned away: nobody approves their own work.
How it works
From one sentence to routed, gated work.
Follow one requirement through the organization. Scroll to move it along.
- Requirement
A plain-language request comes in. Nothing else is needed to start.
- Analyze
Intent, features, and parameters are extracted. Anything left unstated becomes a written assumption, not a silent guess.
- Route to roles
Each task goes to the role whose skills, capabilities, and authority fit it. Routing reads the organization as data.
- Review and gate
Work is executed, then verified by an independent reviewer. Gates such as architecture approval wait for a named human.
- Deliverable
The work product arrives with its trail: who did what, from which inputs, backed by which evidence.
Requirement Create a 4-port AXI-to-NoC bridge.
- axi
- noc
- multi_port
- cdc
- registers
Assumption Clocking was not stated, so CDC work is planned conservatively.
- Interface specification: AXI Senior AXI Interface Architect verified
- Microarchitecture Staff NoC Microarchitect verified
- GATE Architecture approval Chief Architect (human) approved
- RTL: AXI slave interface Senior Interface Design Engineer verified
- RTL: Arbitration Senior Interconnect Design Engineer verified
- Verification plan Senior Verification Planning Engineer verified
- GATE Verification signoff VP, Verification (human) approved
What the organization looks like
A whole company, defined as data.
Every number here is generated from the code at each release.
- 207organizational units
- 685roles, from intern to CEO
- 140skills defined
- 9engineering workflows
- 12constitution principles
- 44verification knowledge packs
- 1987automated tests
- Product
- Architecture
- Design Engineering
- Verification
- Silicon Implementation
- Software
- Security
- Infrastructure
- Documentation
- Quality
The company constitution
Twelve principles the engine enforces.
Each one is a blocking check: an action that breaks it is refused before it changes anything. When an AI worker’s submission is refused, the attempt and the reason are recorded.
-
P1
Traceability
Every task traces to the requirement it serves.
-
P2
Evidence for decisions
Important engineering decisions require evidence.
-
P3
Explicit uncertainty
Agents must explicitly represent uncertainty.
-
P4
No fabricated work
Agents must not fabricate completed work.
-
P5
No fabricated tool runs
No claim that a tool ran unless it did.
-
P6
Independent review
Critical work is reviewed. Nobody approves their own work.
-
P7
Conflicts escalate
Conflicting outputs are escalated before approval.
-
P8
Provenance
Every change records who, what, and from which inputs.
-
P9
Evidence for signoff
Signoff requires evidence.
-
P10
No hidden state changes
Every change goes through the engine and the audit trail.
-
P11
Auditability
The audit trail is append-only and hash-chained.
-
P12
Human approval at gates
Gates can require a human to approve.
Built on VeriTriage
The verification engine inside.
VeriTriage turns simulation logs, coverage, and waveforms into an evidence graph and a ranked, evidence-backed root cause. When IP Nirmaan triages a regression, VeriTriage does the investigation, and its results become evidence in the task.
Status and roadmap
Early, and honest about it.
What works today, what comes next, and what has not happened yet.
Working today
The organization model, planning, routing, reviews, gates, the audit trail, and real VeriTriage investigations. AI workers can take design, RTL, and verification seats. They are off by default. Open-source tools check every RTL submission (lint, simulation, synthesis, and formal proofs when the work includes them) before a person reviews it. On a small block, place and route, three-corner timing, DRC, and LVS run for real in CI. In the tests, the AI workers’ answers are scripted; one early live run of Claude Opus 5.5 passed all four RTL cases, judged by held-out checks, but was not recorded as data.
Next
Recorded, repeated live evaluations that anyone can re-judge, formal proofs written by the AI workers, and physical design beyond small blocks.
Not yet
No customer has received IP from the system, and nothing has been taped out. The reference blocks that run through the whole flow (a register block, a FIFO, an arbiter) prove the flow and its checks, not yet a model designing them unaided. We have no design partners yet.
Design partners
Looking for a few design partners.
IP Nirmaan is early. We are looking for a small number of teams to try it on real work, under written terms.
A small block, with its evidence
Bring the spec for a small, single-clock digital block: a register block, a FIFO, an arbiter, or bus glue on APB or AXI4-Lite. We build it and give you the evidence from open-source tools (lint, simulation, synthesis, and formal), with every log, including what failed. Your engineer signs it off.
A regression, measured
Bring a regression from your simulator, with your own triage labels. We run VeriTriage on your machines, offline, and compare its top diagnosis with your labels, one regression at a time. You see how often it was right.
What we ask
A real requirement, an engineer for a short weekly review, and honest feedback. Work starts only after we agree in writing how your data is handled. Not covered: multi-clock designs, signoff, tapeout, or commercial EDA tools.
Talk to us
Building semiconductor IP? Let's talk about it.
IP Nirmaan is early. Tell us what you're working on, and we'll tell you honestly what it can and can't do for you today.